Because of latency problems with memory accesses, various techniques have been developed to increase the performance of memory read operations. One such technique is known as speculative memory accesses. A speculative memory access is a memory access, not of the data requested by a read operation, but of the data which it is believed may be requested later based upon a current read operation. For example, when a processor requests an instruction from memory it is very likely that the processor will request the next consecutive address or block of addresses in memory as well. Accordingly, a speculative memory access may be executed which retrieves, along with the requested data, the next consecutive data, and stores that data in a buffer to be provided to the processor. Such a speculative memory access can have substantial benefits in increasing performance of a memory system.
As processing systems have evolved, they have often included a number of general purpose and custom designed discrete devices which make up the processing system. These systems typically included a processor and a memory controller. The processor would be a general purpose processor which may be used in a wide variety of systems, but the memory controller was typically custom designed for a particular hardware configuration. In other words, the memory controller in these systems was built with information about the memory structure of the processing system including the acceptable memory addresses and the addresses of any memory mapped input/output ("I/O") devices.
Such systems typically include both well behaved and non-well behaved memory or memory-mapped I/O devices. Well behaved memory is memory, such as RAM or ROM, which when accessed by a read operation multiple times will always provide the same data, until that data is changed by a write operation. Non-well behaved memory is memory which is affected by a read operation or otherwise provides unpredictable results. Examples of non-well behaved memory include First-In First-Out (FIFO) buffers or status registers which automatically change their contents or reset upon being read. For such non-well behaved locations a speculative access could cause the loss of data and/or the delivery of incorrect data if the processor did not intend for the speculatively-accessed location to be accessed yet. Thus, speculative memory accesses must be controlled in a memory environment which includes non-well behaved memory. As used herein, the term "memory" refers to any device from which data may be read and wherein the device is accessed by an address associated with the data to be read.
The processor's in these systems typically have a Memory Management Unit (MMU) function which provides control over whether the processor will make a speculative request to the memory controller. This is accomplished with an MMU which allows the specification of whether each region of memory is well behaved or not. If a region is marked as being well behaved, then the processor may make speculative requests to that region (as well as normal, non-speculative requests). If a region is marked as being non-well behaved then the processor will avoid making speculative requests to that region, and will only make requests that are non-speculative.
Once the processor has decided to make a request, the memory controller may further decide to speculatively access additional data, beyond what was requested by the processor. Again, the problem is the avoidance of the speculative portion of the access if the region being accessed is non-well behaved. Typically, a custom designed memory controller is provided in the discrete system to statically avoid making any speculative access beyond the data which was explicitly requested by the processor. This has been accomplished via built-in "knowledge", within the hardware of the memory controller, of those regions in the system which are non-well behaved. Thus, a custom-designed discrete memory controller device for a predefined system can be designed to avoid making speculative accesses to non-well behaved memory locations and thus avoid losing information or corrupting data.
However, as processing systems have become more and more integrated it has become desirable to incorporate a memory controller and a processor in a single integrated circuit. The integration of the memory controller with the processor can greatly improve the overall performance of the processing system. However, such a general purpose integrated device may be used in any number of systems with varying addresses for non-well behaved locations. The memory controller of the integrated device is difficult to effectively custom-design for each implementation of memory with which it may be used. In such an integrated memory controller, it is no longer possible to build-in knowledge of these varying memory systems, as a means of avoiding speculative access to non-well behaved memory locations.
In view of the above discussion, there exists a need for further advancement in the control of speculative memory accesses and, in particular, for advancements in the control of speculative memory accesses in general purpose integrated devices.